Method and apparatus for implementing multiple lock indicators in a multiprocessor computer system

Abstract From the Canadian patent

A memory node in a computer system having multiple processors interconnected by a pended bus provides exclusive read-modify-write operations employing multiple lock bits. A processor generates an interlock read command which is transmitted as a transfer over the pended bus to the memory node. Acknowledge confirmations are transmitted by the memory back to the processor two bus cycles after each bus cycle of the processor transfer. The processor transfer, including an interlock read command, is stored in a input queue in memory and processes in turn by the memory. A first interlock read command to a specified memory location causes a lock bit to be set for that location and a first type of …