Low current cmos translator circuit

Abstract From the Canadian patent

A low current CMOS translator arrangement is disclosed that utilizes a low current inverting stage having a peak current, requirement, fed by a constant current source at a supply node that also has a capacitor coupled to it. This low current inverter is useful for a number of applications including generating a, sinusoidal signal when it is coupled to a crystal. When one or more are cascaded and coupled to a square wave input signal the, arrangement becomes a low current translator that level-shifts or translates, the input signal having a first voltage range to a translated square wave output signal having a second voltage range. In another embodiment called a low current squaring …