Ic with means for reducing esd damage

Abstract From the Canadian patent

An integrated-circuit (IC) chip having means to prevent or mitigate damage from electrostatic discharge (ESD) employing a thick dielectric coating of insulative oxide between the surface of the chip substrate and the metallization film used to make contact with regions of the substrate. At least a portion of this layer is formed at temperatures below 700°C. The coating is sufficiently thick everywhere that its breakdown voltage is greater than the breakdown voltage of any junction in the substrate. This assures that the breakdown caused by ESD will always occur in the junction which is self healing, rather than in the dielectric coating, where the damage could be permanent.