Parallel processor error checking

Abstract From the Canadian patent

A system for error correction in the reading and writing of data to memory in a multiprocessor environment such as a parallel processor. The data written to and read from memory for each processor is channeled through a single error correcting system which effectively treats the data for plural memories associated with plural processors as a single data word and generates a single error correcting code for that combined data word. By applying a single error correcting methodology to a plurality of memories and associated processors far greater, efficiency is achieved in the parallel processor environment. The read and write operations for the plural memories must be accomplished …