Method for manufacturing wells for cmos transistor circuits separated by insulating trenches
CA 1287692 C · Owner: Neppl, Franz · Inventors: Mazure-Espejo, Carols-A.; Zeller, Christoph; Neppl, Franz
Overview
Its claims, description and drawings are in the Canadian Patents Database.
Open the CIPO recordAbstract From the Canadian patent
A double well CMOS process wherein the wells are separated by insulating trenches introduced into a semiconductor substrate, the position of the insulating trench along the isotropic under-etching in a silicon oxide layer employed together with a silicon nitride layer used as a masking layer in the implantation of the well which is first implanted. The trench itself is produced by anisotropic etching with silicon oxide masks used in the well implantations as etching masks. The trench width is defined with the isotropic etching and the trench depth is defined by the anisotropic etching. In this method both well implanatations and the trench etching are carried out with only one …
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Listed from its CIPO record in Patent Yard's archive of Canadian patents past their term. Its claims, description and drawings are in the CIPO record and on Google Patents, and the Claude kit works from them.
Why it's free to use
- Granted August 13, 1991. A Canadian patent filed before October 1, 1989 lasted 17 years from grant, so its term ended August 13, 2008.
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Timeline
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Sources & verification
Official CIPO records
Everything on this page comes from the CIPO record linked above. Contains information licensed under the Open Government Licence – Canada.