Low power, high noise margin logic gates employing enhancement mode switching fets
CA 1286733 C · Owner: Sitch, John Edward · Inventors: Sitch, John Edward
Overview
Its claims, description and drawings are in the Canadian Patents Database.
Open the CIPO recordAbstract From the Canadian patent
Abstract of the Disclosure A low power, high noise margin logic gate comprises: an input terminal, an output terminal and first, and second voltage supply terminals; an enhancement mode switching FET having a gate connected to the input terminal a source and a drain; a load device connected between the drain of the switching FET and the first voltage supply terminal; a feedback device connected between the source of the switching FET and the second voltage supply terminal; a two terminal level shift device connected between the drain of the switching FET and the output terminal; and an enhancement mode pulldown FET having a gate connected to the source of the switching FET, a source …
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Listed from its CIPO record in Patent Yard's archive of Canadian patents past their term. Its claims, description and drawings are in the CIPO record and on Google Patents, and the Claude kit works from them.
Why it's free to use
- Granted July 23, 1991. A Canadian patent filed before October 1, 1989 lasted 17 years from grant, so its term ended July 23, 2008.
- We check Canadian rights only. A patent in its family in another country could still be in force: check its family on Google Patents.
Timeline
Timeline From CIPO dates
Sources & verification
Official CIPO records
Everything on this page comes from the CIPO record linked above. Contains information licensed under the Open Government Licence – Canada.