Digital timing signal generator and voltage regulator circuit

Abstract From the Canadian patent

A digital timing signal generator and voltage regulator circuit is provided. In one embodiment the circuit includes a delay line. The delay line operating voltage is derived from digitally encoded power/ timing signals transmitted by an isolated logic control circuit. The delay line receives and propagates the digitally encoded signals. Outputs of selected stages of the delay line are tapped to provide multiphasic timing signals for use by associated logic circuits. A plurality of gates having inputs connected to various stages of the delay line receive selected timing signals as they propagate along the delay line. Increases in the operating voltage cause the selected timing signals to …