Microprocessor having separate instruction and data interfaces

Abstract From the Canadian patent

A microprocessor architecture is disclosed having separate very high speed instruction and data interface circuitry for coupling via respective separate vary high speed instruction and data interface buses to respective external instruction cache and data cache circuitry. The microprocessor is comprised of an instruction interface, a data interface and an execution, unit. The instruction interface controls communications with the external instruction cache and couples the instructions from the instruction cache to the microprocessor at very high speed. The data interface controls communications with the external data cache and communicates data bi-directionally at very high speed between …