Dynamic memory refresh gate array circuit
CA 1279730 C · Owner: Bhadriraju, Nataraj · Inventors: Bhadriraju, Nataraj
Overview
Its claims, description and drawings are in the Canadian Patents Database.
Open the CIPO recordAbstract From the Canadian patent
This invention is a dynamic RAM memory refresh circuit for use in conjunction with a microprocessor. In a small telecommunication switching system, a microprocessor shares access to memory with the dynamic RAM refresh circuit. Since circuitry size is of paramount importance, this circuit is suitable for implementation with CMOS gate array technology. Since memory access is shared by the microprocessor and the dynamic RAM refresh circuit, processor through-put in affected. However due to the speed of the dynamic RAM refresh circuit the, microprocessor real-time is degraded only from 2 to 5 percent. A row of dynamic RAM memory is refreshed during each memory access by the refresh circuit, so …
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Listed from its CIPO record in Patent Yard's archive of Canadian patents past their term. Its claims, description and drawings are in the CIPO record and on Google Patents, and the Claude kit works from them.
Why it's free to use
- Granted January 29, 1991. A Canadian patent filed before October 1, 1989 lasted 17 years from grant, so its term ended January 29, 2008.
- We check Canadian rights only. A patent in its family in another country could still be in force: check its family on Google Patents.
Timeline
Timeline From CIPO dates
Sources & verification
Official CIPO records
Everything on this page comes from the CIPO record linked above. Contains information licensed under the Open Government Licence – Canada.