Integrated circuit chip
CA 1270327 C · Owner: University Of Waterloo · Inventors: Eldin, Ali G.; Elmasry, Mohamed I.
Overview
Its claims, description and drawings are in the Canadian Patents Database.
Open the CIPO recordAbstract From the Canadian patent
The disclosed chip is suitable for VLSI dRAMS. The memory cell includes a bipolar transistor a JFET, and, a capacitor. The capacitor comprises a MOSFET which is operated only in the accumulation mode. Each cell requires only three lines. On a p-substrate which, comprises the collector of the bipolar the cell layers, are:- an n-well which comprises the channel of the JFET and the base of the bipolar; a p-region which comprises, the gate of the JFET, the emitter of the bipolar and the, bottom plate of the capacitor; an oxide layer; and a conducting layer; arranged as a vertical stack in that order. The latter two layers are the insulator and the top plate of the capacitor. The source and …
Read the whole patent
Listed from its CIPO record in Patent Yard's archive of Canadian patents past their term. Its claims, description and drawings are in the CIPO record and on Google Patents, and the Claude kit works from them.
Why it's free to use
- Granted June 12, 1990. A Canadian patent filed before October 1, 1989 lasted 17 years from grant, so its term ended June 12, 2007.
- We check Canadian rights only. A patent in its family in another country could still be in force: check its family on Google Patents.
Timeline
Timeline From CIPO dates
Sources & verification
Official CIPO records
Everything on this page comes from the CIPO record linked above. Contains information licensed under the Open Government Licence – Canada.