Method of fabricating a junction field effect transistor
CA 1269764 C · Owner: Gte Laboratories Incorporated · Inventors: Armiento, Craig A.
Overview
Its claims, description and drawings are in the Canadian Patents Database.
Open the CIPO recordAbstract From the Canadian patent
Method of fabricating a junction field effect transistor, specifically a static induction transistor which may be of GaAs. Elongated N-type source regions are formed in an N-type epitaxial layer of semiconductor material grown on a substrate. A tri-level mask is formed having elongated openings exposing portions o the epitaxial layer intermediate between the source regions. The openings are wider at the bottom than at the top. P-type gate regions are formed by ion-implanting P-type doping material through the mask openings. Silicon dioxide is deposited through the openings by angle evaporation to form generally trapezoidal-shaped temporary gate members over the gate regions. The tri-level …
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Listed from its CIPO record in Patent Yard's archive of Canadian patents past their term. Its claims, description and drawings are in the CIPO record and on Google Patents, and the Claude kit works from them.
Why it's free to use
- Granted May 29, 1990. A Canadian patent filed before October 1, 1989 lasted 17 years from grant, so its term ended May 29, 2007.
- We check Canadian rights only. A patent in its family in another country could still be in force: check its family on Google Patents.
Timeline
Timeline From CIPO dates
Sources & verification
Official CIPO records
Everything on this page comes from the CIPO record linked above. Contains information licensed under the Open Government Licence – Canada.