High speed bit interleaved time division multiplexer for multinode communication systems

Abstract From the Canadian patent

A bit interleaved time division multiplexer for multinode systems is disclosed and comprises: a high speed bus; at least two aggregate common means each aggregate, common means including aggregate common address recognition, means recoding means for obtaining information according to a first frame over an aggregate, supplying an intramultiplexer system address for at least one bit of said obtained information, and sending said information accompanied by said intramultiplexer system address onto said high speed bus aggregate common decoding means and transmit multiplexing means for receiving bits of information from said high speed bus, for multiplexing said information according to a second …