Method and apparatus for addressing a memory by array transformations

Abstract From the Canadian patent

A memory having an address generator in an intelligent port which generates address sequences specified by an array transformation operator in a programmable processor thereby, allowing a controlling processor to proceed immediately to the preparation of the next instruction in parallel with memory execution of a present instruction. The intelligent port of the memory creates complex data structures from input data arrays stored in memory and directs the transformation of the data structures into output data streams. The memory comprises a plurality of read-write memory banks and a bank of read-only memory interconnected through intelligent ports and busses to other units of the processor. …