Digital processor for convolution and correlation

Abstract From the Canadian patent

A digital processor is provided for performing an N-point convolution or correlation of q-bit coefficients with data words guard band extended to p bits. The processor includes an array of one-bit clockactivated gated full adder cells arranged in N rows and q columns. Each cell is arranged to input data> carry and cumulative sum bits and to output the data bit and new carry and cumulative sum bits corresponding to the product of the input data bit with a respective stationary coefficient bit. The output carry bit is recirculated on the respective cell. Cumulative sum generation is cascaded down array columns. Data moves along each row and thence to the next lower row via delaying means …