Verification of on-line fault monitor performance

Abstract From the Canadian patent

Proper operation of a system fault monitor is verified while the monitor is coupled on-line with the system and to an alarm line. During periods when actual system signals are produced, the monitor is coupled through one of two time delay circuits to the alarm line. During periods when no actual signals are produced by the system, the monitor input is switched to an error signal generator and the monitor output is coupled through the other time delay circuit to processing circuitry which detects the presence of the alarm signal after the circuit time delay. If no alarm signal is detected, a failure of the monitor and/or delay circuit is indicated.