Bus control gate array
CA 1252575 A · Owner: Data General Corporation · Inventors: Arima, Shigemi; Wadano, Yoshihiko; Miyashita, Kazuhiro
Overview
Its claims, description and drawings are in the Canadian Patents Database.
Open the CIPO recordAbstract From the Canadian patent
Abstract of the Disclosure, In a computer having a central processing unit (CPU), a common bus, a plurality of input and output devices which are connected to the common bus and which have an intrinsic I/O device address, individually and, a bus control gate array, the bus control gate array according to the present invention includes an I/O device address decoder. The I/O device address decoder comprises a plurality of gates and decodes an I/O device address supplied from the CPU to produce a control signal for selecting the designated I/O device thereto.
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Listed from its CIPO record in Patent Yard's archive of Canadian patents past their term. Its claims, description and drawings are in the CIPO record and on Google Patents, and the Claude kit works from them.
Why it's free to use
- Granted April 11, 1989. A Canadian patent filed before October 1, 1989 lasted 17 years from grant, so its term ended April 11, 2006.
- We check Canadian rights only. A patent in its family in another country could still be in force: check its family on Google Patents.
Timeline
Timeline From CIPO dates
Sources & verification
Official CIPO records
Everything on this page comes from the CIPO record linked above. Contains information licensed under the Open Government Licence – Canada.