Integrated semiconductor circuit including a tantalum silicide diffusion barrier

Abstract From the Canadian patent

An integrated semiconductor circuit consisting of a silicon substrate having an impurity doped circuit therein and a, layer of silicon dioxide formed on the substrate and having a contact hole therein overlying the circuit. An outer contact interconnect level composed of aluminum or an aluminum alloy provides electrical contact to the circuit. A tantalum disilicide diffusion barrier layer is disposed between the circuit and the interconnect level, with a layer of substantially pure tantalum both above and below the tantalum disilicide diffusion barrier layer.