Sequential logic integrated circuit for pcm compression

Abstract From the Canadian patent

A sequential logic circuit for providing PCM compression in an integrated circuit includes a first shift register having both serial and parallel outputs for receiving an uncompressed PCM word having a sign bit followed by a variable number of zeros and then a number of significant bits, a second shift register for outputting a compressed PCM word, a time base generating bit rate clock signals for shifting said registers, a counting circuit for counting bits for so long as zeros are shifted serially out of the first register, after ignoring the sign bit the counting circuit having a maximum count and control, logic for first enabling shifting of the first register until the zeros or an …