Dynamic random access memory refresh control system

Abstract From the Canadian patent

Abstract of the Disclosure, A system and method are disclosed for automatically refreshing a dynamic random access memory (DRAM) under a plurality of different operational conditions of an associated processor. In a preferred embodiment of the invention when the, processor is normally executing instructions it generates active signals. These active signals enable a generator circuit to generate timing signals. A hidden refresh circuit uses status signals and a first part of these timing signals to generate a refresh pulse during an opcode fetch cycle of each instruction being executed by the processor. A control circuit uses each refresh pulse and a second part of the timing signals to …