Bit serial convolutional decoder for vlsi implementation

Abstract From the Canadian patent

27284-3?, ABSTRACT, A decoder for forward-error-correcting (FEC) convolutional codes. The decoder uses the Viterbi algorithm for decoding the rate ?,constraint length 7 code with generator polynomials x6+x5+ x3+x2+1, and x6+x3+x2+x+1. The architecture of the instant decoder is appropriate for implementation on a single monolithic VLSI integrated circuit chip and includes a branch metric calculator circuit which produces output signals representative of input symbol signals. These output signals are supplied to a metric update circuit which evaluates the signals from the calculator circuit and provides decisions to a path update circuit which converges the signals thereto and the output …