Parallel cyclic redundancy checking circuit

Abstract From the Canadian patent

A parallel cyclic redundancy checking circuit which determines the validity of digital binary, cyclical data. The parallel structure of this circuit enables it to check high frequency data. Shift registers store sequentially occurring parallel groups of data and a feedback network comprising exclusiveor gates provides a coding arrangement which produces a resultant data pattern to indicate the validity of the cyclical parallel input data. Resultant data patterns are periodically stored in a random-accessmemory which initializes the shift registers to provide a time sharing operation. A comparator detects invalid data by comparing the resultant patterns with expected values.