Memory with error checking and correcting device with selective intervention

Abstract From the Canadian patent

A data processing apparatus having a main memory with a plurality of addressable locations includes a device for error code generation, error comparison and correction which controls the read-out of information only in cases where error-affected memory locations are addressed, the readout of information from all other locations being unaffected and performed at the maximum operating speed. The memory has timing and control circuits which modify the duration of the memory cycle depending upon the presence or absence of errors. The control of read-out is systematically performed after each reading operation the in-, formation read-out being checked and if affected by error, corrected before …