Double bit error correction using single bit error correction, double bit error detection logic and syndrome bit memory

Abstract From the Canadian patent

A method of, and an apparatus for, obtaining double bit error correction capabilities in a large scale integrated (LSI) semiconductor memory system using only single bit error correction, double bit error detection (SEC DED) logic are, disclosed. The method is based upon the statistical assumption that in a large scale integrated semiconductor memory substan-, tially all errors in the data bits that make up a data word are initially a single bit error and that increasing multiple i.e. double, triple, etc. bit errors occur in a direct increasing ratio of the use or selection of the data word. In the present invention, all data words are priorly tested to be error free. Subsequent detection …