Microprocessor architecture with integrated interrupts and cycle steals prioritized channel

Abstract From the Canadian patent

Abstract, A computing system architecture includes a central processing unit having a channel, arithmetic and logic unit a plurality of working, registers, and control logic; a plurality of local storage registers; a main storage; an executable control store; one or more input/output devices; and a multiplexed cycle steal and interrupt request common poll bus. The storage and input/output devices communicate with and are controlled by the central processing unit over a looped or unidirectional, bus and control channel including a bus in a bus out, an address and, control bus and a plurality of control lines. Bus out is operated to address the executable control store and main storage and to …