Multi-instruction stream branch processing mechanism

Abstract From the Canadian patent

In a high-performance computer which prefetches and predecodes instructions for sequential presentation to an execution unit, at least three separately gated and sequenced instruction buffers for prefetched instructions permit continued sequential predecoding and buffering of instructions from three independent instruction streams identified by multiple branch instructions some, of which may be conditionally executed. A number of pointers identify a particular one of the multiple instruction buffers. A first pointer identifies one of the instruction buffers which is to receive the target instruction identified by a branch instruction decoded from another instruction stream contained in …