Circuits and methods for multiple control data processing systems

Abstract From the Canadian patent

Abstract of the Disclosure, In a data processing system in which two or more asynchronous processors operating as masters interchange requests and responses with a control unit that in turn controls a number of peripheral devices and operates as a slave to the processors, repetitive requests from a high speed processor can give rise to an impasse condition in which the control unit is blocked from completing the previously initiated sequence between a peripheral device and another processor. In accordance with the invention the, interface between the processors and the peripheral devices incorporates means which detect an uninterrupted sequence of predetermined length, of busy responses …