Level sensitive embedded array logic system

Abstract From the Canadian patent

Abstract, A generalized and modular logic system is described for all arithmetic/logical units and their associated control storage and any other arrays. The logic system is partitioned into sections formed of combinational logic networks, storage circuitry, and arrays. The storage circuitry is sequential in operation and employs clocked dc latches. Two or more synchronous, non-overlapping independent system clock trains are used to control the latches. The array is a rectangular array of storage element, M x N where, M is the number of words in the array and N is the number of bits in each word. The array may be read only, or it may be a read/write array. The array may be a programmable …