Enhancement-mode fets and depletion-mode fets with two layers of polycrystalline silicon
CA 1088676 A · Owner: International Business Machines Corporation · Inventors: Rideout, Vincent L.
Overview
Its claims, description and drawings are in the Canadian Patents Database.
Open the CIPO recordAbstract From the Canadian patent
Abstract of the Disclosure, Enhancement-mode field-effect transistors (FETs) and depletion-mode FETs are provided on the same semiconductive substrate using five basic, lithographic pattern-, delineating steps. The five lithographic masking steps delineate in order:, (1) the field isolation regions; (2) the enhancement-mode FET gate, electrodes; (3) the depletion-mode FET gate electrodes; (4) contact holes or vias to FET source and drain regions and to depletion-, mode FET gates; and (5) the high electrical conductivity, metallic-type interconnection pattern. The low-concentration doping required to form the depletionmode channel regions is provided after the second but before the third …
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Listed from its CIPO record in Patent Yard's archive of Canadian patents past their term. Its claims, description and drawings are in the CIPO record and on Google Patents, and the Claude kit works from them.
Why it's free to use
- Granted October 28, 1980. A Canadian patent filed before October 1, 1989 lasted 17 years from grant, so its term ended October 28, 1997.
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Timeline
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Official CIPO records
Everything on this page comes from the CIPO record linked above. Contains information licensed under the Open Government Licence – Canada.