Fail-safe electronic time delay circuit

Abstract From the Canadian patent

This disclosure relates to a fail-safe time delay circuit for providing a definite time interval. The time delay circuit includes a resistance-capacitance charging network which is connected to a source of a d.c. supply source by a switching device. The potential charge developed on the capacitor powers an inverter to produce a.c. signals having a given frequency. The a.c. signal is fed to a multi-stage tuned amplifier having a resonant circuit tuned to the given frequency. The amplified a.c. signals are applied to a voltage doubling network which normally energizes a load and which maintains the load energized for no longer than the definite time interval after the opening of the switching …