Circuit for implementing a modified lru replacement algorithm for a cache

Abstract From the Canadian patent

Abstract of the Disclosure The invention operates with a storage hierarchy buffer such as a cache, with an LRU network which utilizes two array memory chips, array selection and addressing controls, chronology controls, next LRU addressing circuits and mode controls for controlling the different types of operations needed by the LRU network. Each time a different block is accessed in the cache a next use, value is generated in a chronology register in the chronology controls, and the new use value is written into the active one of the arrays at a position which corresponds to the position of the block to be replaced in the cache. An LRU determination is made when a cache miss occurs by …