Fet device with reduced overlap capacitance and method of manufacture

Abstract From the Canadian patent

A metal gate transistor is fabricated to have reduced gate overlap of source/drain regions and increased oxide thickness over the diffused regions whereby parasitic capacitance is reduced and switching speed is increased. The method comprises the steps of (1) selecting an appropriate insulating thickness over a semiconductor substrate (2) forming source/drain diffused regions in the substrate through openings in the insulating layer at appropriate diffusion temperatures, (3) selecting an appropriate drivein and regrowth temperature whereby the insulating layer thickness over the diffused region is greater than that over the non-diffused region and out diffusion of the diffused regions is …