Bias circuit for fet

Abstract From the Canadian patent

A bias circuit particularly adapted for use with a field effect transistor whereby the-drain bias current of the field effect transistor is maintained constant in the event of fluctuations in the operating voltage applied to the field effect transistor by a power supply. The bias circuit changes the gate bias voltage applied to the FET as a function of the fluctuations in the operating voltage to thereby restore the drain bias current to a constant value. A variable impedance is included in the bias circuit, the variable impedance being voltage dependent such that its impedance varies as the voltage applied thereto varies in accordance with a hyperbolic relation. The voltage applied to the …